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| author | David Goodwin <david_goodwin@apple.com> | 2009-08-05 21:02:22 +0000 |
|---|---|---|
| committer | David Goodwin <david_goodwin@apple.com> | 2009-08-05 21:02:22 +0000 |
| commit | 7bfdca0206f51132b26094c6f83a5ac97ee0f943 (patch) | |
| tree | 39de3c9105f7f3686908906782aaf2182281ec3d /lib/Target/ARM/ARMInstrNEON.td | |
| parent | a5bb59f85613e8ce481351803e7388f5ab466e72 (diff) | |
| download | external_llvm-7bfdca0206f51132b26094c6f83a5ac97ee0f943.zip external_llvm-7bfdca0206f51132b26094c6f83a5ac97ee0f943.tar.gz external_llvm-7bfdca0206f51132b26094c6f83a5ac97ee0f943.tar.bz2 | |
When using NEON for single-precision FP, the NEON result must be placed in D0-D15 as these are the only D registers with S subregs. Introduce a new regclass to represent D0-D15 and use it in the NEON single-precision FP patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78244 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrNEON.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 5cf81ee..d31ec41 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -285,9 +285,11 @@ class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, // Basic 2-register operations, scalar single-precision class N2VDInts<SDNode OpNode, NeonI Inst> : NEONFPPat<(f32 (OpNode SPR:$a)), - (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), - SPR:$a, arm_ssubreg_0)), - arm_ssubreg_0)>; + (EXTRACT_SUBREG (COPY_TO_REGCLASS + (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), + SPR:$a, arm_ssubreg_0)), + DPR_VFP2), + arm_ssubreg_0)>; // Narrow 2-register intrinsics. class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, @@ -329,11 +331,13 @@ class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, // Basic 3-register operations, scalar single-precision class N3VDs<SDNode OpNode, NeonI Inst> : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)), - (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), - SPR:$a, arm_ssubreg_0), - (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), - SPR:$b, arm_ssubreg_0)), - arm_ssubreg_0)>; + (EXTRACT_SUBREG (COPY_TO_REGCLASS + (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), + SPR:$a, arm_ssubreg_0), + (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), + SPR:$b, arm_ssubreg_0)), + DPR_VFP2), + arm_ssubreg_0)>; // Basic 3-register intrinsics, both double- and quad-register. class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, @@ -375,12 +379,14 @@ class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, class N3VDMulOps<SDNode MulNode, SDNode OpNode, NeonI Inst> : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))), - (EXTRACT_SUBREG (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), - SPR:$acc, arm_ssubreg_0), - (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), - SPR:$a, arm_ssubreg_0), - (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), - SPR:$b, arm_ssubreg_0)), + (EXTRACT_SUBREG (COPY_TO_REGCLASS + (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), + SPR:$acc, arm_ssubreg_0), + (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), + SPR:$a, arm_ssubreg_0), + (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), + SPR:$b, arm_ssubreg_0)), + DPR_VFP2), arm_ssubreg_0)>; // Neon 3-argument intrinsics, both double- and quad-register. |