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| author | Jim Grosbach <grosbach@apple.com> | 2010-09-14 23:54:06 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2010-09-14 23:54:06 +0000 |
| commit | c7a331ca4ffaba39818d72131c9a55bfcf133242 (patch) | |
| tree | 11316a778d297f2a31eff479eed921642b82e5d6 /lib/Target/ARM/ARMInstrNEON.td | |
| parent | 188c1aa1c6b9ab51fdc311c93451e5342d85637c (diff) | |
| download | external_llvm-c7a331ca4ffaba39818d72131c9a55bfcf133242.zip external_llvm-c7a331ca4ffaba39818d72131c9a55bfcf133242.tar.gz external_llvm-c7a331ca4ffaba39818d72131c9a55bfcf133242.tar.bz2 | |
Reapply r113875 with additional cleanups.
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrNEON.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 9e79047..6937392 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -218,9 +218,9 @@ class VLD1DWB<bits<4> op7_4, string Dt> "vld1", Dt, "\\{$dst\\}, $addr$offset", "$addr.addr = $wb", []>; class VLD1QWB<bits<4> op7_4, string Dt> - : NLdSt<0,0b10,0b1010,op7_4, (outs QPR:$dst, GPR:$wb), + : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$dst1, DPR:$dst2, GPR:$wb), (ins addrmode6:$addr, am6offset:$offset), IIC_VLD2, - "vld1", Dt, "${dst:dregpair}, $addr$offset", + "vld1", Dt, "\\{$dst1, $dst2\\}, $addr$offset", "$addr.addr = $wb", []>; def VLD1d8_UPD : VLD1DWB<0b0000, "8">; @@ -675,8 +675,9 @@ class VST1DWB<bits<4> op7_4, string Dt> "vst1", Dt, "\\{$src\\}, $addr$offset", "$addr.addr = $wb", []>; class VST1QWB<bits<4> op7_4, string Dt> : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb), - (ins addrmode6:$addr, am6offset:$offset, QPR:$src), IIC_VST, - "vst1", Dt, "${src:dregpair}, $addr$offset", "$addr.addr = $wb", []>; + (ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2), + IIC_VST, "vst1", Dt, "\\{$src1, $src2\\}, $addr$offset", + "$addr.addr = $wb", []>; def VST1d8_UPD : VST1DWB<0b0000, "8">; def VST1d16_UPD : VST1DWB<0b0100, "16">; |