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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-18 21:50:53 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-18 21:50:53 +0000 |
| commit | 93b3eff62322803a520e183fdc294bffd6d99bfa (patch) | |
| tree | 4cd6de7ba49f9322993c3f4ca1c4f30c6fa27920 /lib/Target/ARM/ARMInstrThumb.td | |
| parent | b48ef3a3ec7f527b0c76e7fbb37bbaac63b7c6aa (diff) | |
| download | external_llvm-93b3eff62322803a520e183fdc294bffd6d99bfa.zip external_llvm-93b3eff62322803a520e183fdc294bffd6d99bfa.tar.gz external_llvm-93b3eff62322803a520e183fdc294bffd6d99bfa.tar.bz2 | |
Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 2b04727..199691f 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -683,8 +683,8 @@ multiclass thumb_ldst_mult<string asm, InstrItinClass itin, InstrItinClass itin_upd, bits<6> T1Enc, bit L_bit, string baseOpc> { def IA : - T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), - itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>, + T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), + itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>, T1Encoding<T1Enc> { bits<3> Rn; bits<8> regs; @@ -696,7 +696,7 @@ multiclass thumb_ldst_mult<string asm, InstrItinClass itin, InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, "$Rn = $wb", itin_upd>, PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA")) - GPR:$Rn, pred:$p, reglist:$regs)> { + tGPR:$Rn, pred:$p, reglist:$regs)> { let Size = 2; let OutOperandList = (outs GPR:$wb); let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); @@ -720,6 +720,11 @@ defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, } // neverHasSideEffects +def : InstAlias<"ldm${p} $Rn!, $regs", + (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, + Requires<[IsThumb, IsThumb1Only]>; + + let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), IIC_iPop, |