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| author | Amara Emerson <amara.emerson@arm.com> | 2013-09-23 14:26:15 +0000 |
|---|---|---|
| committer | Amara Emerson <amara.emerson@arm.com> | 2013-09-23 14:26:15 +0000 |
| commit | 0f22c134be40a337b30e30bdafb9e8b6880dea1e (patch) | |
| tree | ee7c130b4490da27bc30ec31721a7f9613964c57 /lib/Target/ARM/ARMInstrThumb2.td | |
| parent | baca5334db904819e6c0d26cd5f5203f82c44f6e (diff) | |
| download | external_llvm-0f22c134be40a337b30e30bdafb9e8b6880dea1e.zip external_llvm-0f22c134be40a337b30e30bdafb9e8b6880dea1e.tar.gz external_llvm-0f22c134be40a337b30e30bdafb9e8b6880dea1e.tar.bz2 | |
[ARM] Split A/R class into separate subtarget features.
Patch by Bradley Smith.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191202 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb2.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 435b0ea..fcc8f86 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -3922,7 +3922,7 @@ defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">; // // A/R class can only move from CPSR or SPSR. def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", - []>, Requires<[IsThumb2,IsARClass]> { + []>, Requires<[IsThumb2,IsNotMClass]> { bits<4> Rd; let Inst{31-12} = 0b11110011111011111000; let Inst{11-8} = Rd; @@ -3932,7 +3932,7 @@ def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>; def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", - []>, Requires<[IsThumb2,IsARClass]> { + []>, Requires<[IsThumb2,IsNotMClass]> { bits<4> Rd; let Inst{31-12} = 0b11110011111111111000; let Inst{11-8} = Rd; @@ -3965,7 +3965,7 @@ def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary, // the mask with the fields to be accessed in the special register. def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn), NoItinerary, "msr", "\t$mask, $Rn", []>, - Requires<[IsThumb2,IsARClass]> { + Requires<[IsThumb2,IsNotMClass]> { bits<5> mask; bits<4> Rn; let Inst{31-21} = 0b11110011100; |