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| author | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-05 11:10:31 +0000 |
|---|---|---|
| committer | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-05 11:10:31 +0000 |
| commit | 10b5086e6e945b830ff909821240eff5c4a42bfc (patch) | |
| tree | c7480522b0cf9d0240672fae665b76dadc4f9da0 /lib/Target/ARM/ARMInstrThumb2.td | |
| parent | 16277c4698f36a756c540fae326874774156aaed (diff) | |
| download | external_llvm-10b5086e6e945b830ff909821240eff5c4a42bfc.zip external_llvm-10b5086e6e945b830ff909821240eff5c4a42bfc.tar.gz external_llvm-10b5086e6e945b830ff909821240eff5c4a42bfc.tar.bz2 | |
ARM: Add GPR register class excluding LR for use with the ADR instruction.
This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target.
Patch by Daniel Stewart!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190043 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrThumb2.td')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 5d0c484..2f3fa63 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1233,7 +1233,7 @@ let neverHasSideEffects = 1, isReMaterializable = 1 in def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; let hasSideEffects = 1 in -def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd), +def t2LEApcrelJT : t2PseudoInst<(outs jtGPR:$Rd), (ins i32imm:$label, nohash_imm:$id, pred:$p), 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; |