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authorArnold Schwaighofer <aschwaighofer@apple.com>2013-06-04 22:35:17 +0000
committerArnold Schwaighofer <aschwaighofer@apple.com>2013-06-04 22:35:17 +0000
commit8a227084a5b07fa289c34f2b36e12f75b47473d6 (patch)
tree4fa9ffce7f9c6410f47c76bcd24b29136ec53e45 /lib/Target/ARM/ARMInstrVFP.td
parentf500aa0b2465152d1bae390e4d4a48e3a17e85a5 (diff)
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Revert series of sched model patches until I figure out what is going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrVFP.td')
-rw-r--r--lib/Target/ARM/ARMInstrVFP.td6
1 files changed, 2 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index c79ffdd..2380528 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -870,8 +870,7 @@ let Constraints = "$a = $dst" in {
class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
bit op5, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
- : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
- Sched<[WriteCvtFP]> {
+ : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
bits<5> dst;
// if dp_operation then UInt(D:Vd) else UInt(Vd:D);
let Inst{22} = dst{0};
@@ -882,8 +881,7 @@ class AVConv1XInsS_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
class AVConv1XInsD_Encode<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4,
bit op5, dag oops, dag iops, InstrItinClass itin,
string opc, string asm, list<dag> pattern>
- : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern>,
- Sched<[WriteCvtFP]> {
+ : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
bits<5> dst;
// if dp_operation then UInt(D:Vd) else UInt(Vd:D);
let Inst{22} = dst{4};