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authorJoey Gouly <joey.gouly@arm.com>2013-07-09 11:03:21 +0000
committerJoey Gouly <joey.gouly@arm.com>2013-07-09 11:03:21 +0000
commit8dc741d29f9c9beff8a9f26ff23b307b9df4f8fd (patch)
treeb6b5f1ad0938ff6d38e96a21a25c8236ed22bf24 /lib/Target/ARM/ARMInstrVFP.td
parentf27b46b26f86db50ed59769700845f6c589f1dae (diff)
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Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185926 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMInstrVFP.td')
-rw-r--r--lib/Target/ARM/ARMInstrVFP.td21
1 files changed, 21 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index 27f1578..4ee41e8 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -648,6 +648,27 @@ def VNEGS : ASuIn<0b11101, 0b11, 0b0001, 0b01, 0,
let D = VFPNeonA8Domain;
}
+multiclass vrint_inst_zrx<string opc, bit op, bit op2> {
+ def S : ASuI<0b11101, 0b11, 0b0110, 0b11, 0,
+ (outs SPR:$Sd), (ins SPR:$Sm),
+ NoItinerary, !strconcat("vrint", opc), ".f32\t$Sd, $Sm",
+ []>, Requires<[HasV8FP]> {
+ let Inst{7} = op2;
+ let Inst{16} = op;
+ }
+ def D : ADuI<0b11101, 0b11, 0b0110, 0b11, 0,
+ (outs DPR:$Dd), (ins DPR:$Dm),
+ NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
+ []>, Requires<[HasV8FP]> {
+ let Inst{7} = op2;
+ let Inst{16} = op;
+ }
+}
+
+defm VRINTZ : vrint_inst_zrx<"z", 0, 1>;
+defm VRINTR : vrint_inst_zrx<"r", 0, 0>;
+defm VRINTX : vrint_inst_zrx<"x", 1, 0>;
+
def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
(outs DPR:$Dd), (ins DPR:$Dm),
IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",