diff options
| author | Hal Finkel <hfinkel@anl.gov> | 2013-08-03 12:25:10 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-08-03 12:25:10 +0000 |
| commit | 5cad12d12a823d258fc60e3975ffa142d0e190ef (patch) | |
| tree | a993d917c490d00f4497dc874c86427474de6a55 /lib/Target/ARM/ARMJITInfo.h | |
| parent | 6b4dde71cfdcb2e1f2105dd8a677c14d8c3bb4b4 (diff) | |
| download | external_llvm-5cad12d12a823d258fc60e3975ffa142d0e190ef.zip external_llvm-5cad12d12a823d258fc60e3975ffa142d0e190ef.tar.gz external_llvm-5cad12d12a823d258fc60e3975ffa142d0e190ef.tar.bz2 | |
Fix PPC64 64-bit GPR inline asm constraint matching
Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the
64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with
explicit register names, on PPC64 when an i64 MVT has been requested, we need
to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent)
registers.
At some point, we'll probably want to arrange things so that the generic code
in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order
to match these inline asm register constraints. If we do that, this change can
be reverted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187693 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMJITInfo.h')
0 files changed, 0 insertions, 0 deletions