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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2007-04-16 18:10:23 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2007-04-16 18:10:23 +0000 |
| commit | bed2946a96ecb15b0b636fa74cb26ce61b1c648e (patch) | |
| tree | 52a39df658d308bd7dfb4f04479139d23c149c73 /lib/Target/ARM/ARMRegisterInfo.cpp | |
| parent | 892299ccf41e9b3726b1a9f297e47ce636b197ca (diff) | |
| download | external_llvm-bed2946a96ecb15b0b636fa74cb26ce61b1c648e.zip external_llvm-bed2946a96ecb15b0b636fa74cb26ce61b1c648e.tar.gz external_llvm-bed2946a96ecb15b0b636fa74cb26ce61b1c648e.tar.bz2 | |
Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index bf6adbd..0942007 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -1372,7 +1372,7 @@ static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { } void ARMRegisterInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { + MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert((MBBI->getOpcode() == ARM::BX_RET || MBBI->getOpcode() == ARM::tBX_RET || |