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author | Evan Cheng <evan.cheng@apple.com> | 2007-03-20 08:09:38 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-03-20 08:09:38 +0000 |
commit | bf2c8b3c96f5c885095a10b0fcb29438f92d73c2 (patch) | |
tree | e29fe6ae443de3ff4bc386753587aa3654a67ba8 /lib/Target/ARM/ARMRegisterInfo.cpp | |
parent | a16b7cb1d3a482a28bc8f73433f0034d8d8673d7 (diff) | |
download | external_llvm-bf2c8b3c96f5c885095a10b0fcb29438f92d73c2.zip external_llvm-bf2c8b3c96f5c885095a10b0fcb29438f92d73c2.tar.gz external_llvm-bf2c8b3c96f5c885095a10b0fcb29438f92d73c2.tar.bz2 |
Added MRegisterInfo hook to re-materialize an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.cpp')
-rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 51 |
1 files changed, 35 insertions, 16 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 2cc9da6..abc0ad8 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -195,6 +195,38 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, abort(); } +/// emitLoadConstPool - Emits a load from constpool to materialize the +/// specified immediate. +static void emitLoadConstPool(MachineBasicBlock &MBB, + MachineBasicBlock::iterator &MBBI, + unsigned DestReg, int Val, + const TargetInstrInfo &TII, bool isThumb) { + MachineFunction &MF = *MBB.getParent(); + MachineConstantPool *ConstantPool = MF.getConstantPool(); + Constant *C = ConstantInt::get(Type::Int32Ty, Val); + unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); + if (isThumb) + BuildMI(MBB, MBBI, TII.get(ARM::tLDRcp), DestReg).addConstantPoolIndex(Idx); + else + BuildMI(MBB, MBBI, TII.get(ARM::LDRcp), DestReg).addConstantPoolIndex(Idx) + .addReg(0).addImm(0); +} + +void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, + const MachineInstr *Orig) const { + if (Orig->getOpcode() == ARM::MOVi2pieces) { + emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImmedValue(), + TII, false); + return; + } + + MachineInstr *MI = Orig->clone(); + MI->getOperand(0).setReg(DestReg); + MBB.insert(I, MI); +} + /// isLowRegister - Returns true if the register is low register r0-r7. /// static bool isLowRegister(unsigned Reg) { @@ -410,19 +442,6 @@ static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, return NumMIs; } -/// emitLoadConstPool - Emits a load from constpool to materialize NumBytes -/// immediate. -static void emitLoadConstPool(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned DestReg, int NumBytes, - const TargetInstrInfo &TII) { - MachineFunction &MF = *MBB.getParent(); - MachineConstantPool *ConstantPool = MF.getConstantPool(); - Constant *C = ConstantInt::get(Type::Int32Ty, NumBytes); - unsigned Idx = ConstantPool->getConstantPoolIndex(C, 2); - BuildMI(MBB, MBBI, TII.get(ARM::tLDRpci), DestReg).addConstantPoolIndex(Idx); -} - /// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize /// a destreg = basereg + immediate in Thumb code. Materialize the immediate /// in a register using mov / mvn sequences or load the immediate from a @@ -459,7 +478,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, BuildMI(MBB, MBBI, TII.get(ARM::tNEG), LdReg) .addReg(LdReg, false, false, true); } else - emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII); + emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, TII, true); // Emit add / sub. int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); @@ -885,7 +904,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, TII); + emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true); UseRR = true; } } else @@ -920,7 +939,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,Offset,false,TII); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, TII); + emitLoadConstPool(MBB, II, TmpReg, Offset, TII, true); UseRR = true; } } else |