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author | Lang Hames <lhames@gmail.com> | 2012-03-06 00:19:55 +0000 |
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committer | Lang Hames <lhames@gmail.com> | 2012-03-06 00:19:55 +0000 |
commit | 4f92b5e6163b16d63eb63269c2aec670b55ea19a (patch) | |
tree | 964b85f11ba8de9367f99501d06a22d7f7166755 /lib/Target/ARM/ARMRegisterInfo.td | |
parent | 923bb4117a13eac03a6ff630a108829ab767d519 (diff) | |
download | external_llvm-4f92b5e6163b16d63eb63269c2aec670b55ea19a.zip external_llvm-4f92b5e6163b16d63eb63269c2aec670b55ea19a.tar.gz external_llvm-4f92b5e6163b16d63eb63269c2aec670b55ea19a.tar.bz2 |
Split fpscr into two registers: FPSCR and FPSCR_NZCV.
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.td')
-rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index b16a12c..bbd8c92 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -153,11 +153,16 @@ def Q15 : ARMReg<15, "q15", [D30, D31]>; } // Current Program Status Register. -def CPSR : ARMReg<0, "cpsr">; -def APSR : ARMReg<1, "apsr">; -def SPSR : ARMReg<2, "spsr">; -def FPSCR : ARMReg<3, "fpscr">; -def ITSTATE : ARMReg<4, "itstate">; +// We model fpscr with two registers: FPSCR models the control bits and will be +// reserved. FPSCR_NZCV models the flag bits and will be unreserved. +def CPSR : ARMReg<0, "cpsr">; +def APSR : ARMReg<1, "apsr">; +def SPSR : ARMReg<2, "spsr">; +def FPSCR : ARMReg<3, "fpscr">; +def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> { + let Aliases = [FPSCR]; +} +def ITSTATE : ARMReg<4, "itstate">; // Special Registers - only available in privileged mode. def FPSID : ARMReg<0, "fpsid">; |