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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-24 17:46:13 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-24 17:46:13 +0000 |
| commit | 5b81584f7403ffdb9cc6babaaeb0411c080e0f81 (patch) | |
| tree | 6f24c77253dbee60cb277956807ca71d2ff707f7 /lib/Target/ARM/ARMRegisterInfo.td | |
| parent | e234d02204e0e546c3555e7e894b8521d22a2121 (diff) | |
| download | external_llvm-5b81584f7403ffdb9cc6babaaeb0411c080e0f81.zip external_llvm-5b81584f7403ffdb9cc6babaaeb0411c080e0f81.tar.gz external_llvm-5b81584f7403ffdb9cc6babaaeb0411c080e0f81.tar.bz2 | |
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMRegisterInfo.td')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index cf3d668..50f9259 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -225,6 +225,13 @@ def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> { }]; } +// GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the +// implied SP argument list. +// FIXME: It would be better to not use this at all and refactor the +// instructions to not have SP an an explicit argument. That makes +// frame index resolution a bit trickier, though. +def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>; + // restricted GPR register class. Many Thumb2 instructions allow the full // register range for operands, but have undefined behaviours when PC // or SP (R13 or R15) are used. The ARM ISA refers to these operands |