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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-03-26 15:14:04 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-03-26 15:14:04 +0000 |
| commit | afaeb8152c79a9f3c157a614331d6919a0a0fa6a (patch) | |
| tree | 5962a3a26693d4d02744b16c9e809094b6234d56 /lib/Target/ARM/ARMSchedule.td | |
| parent | d6f5a581ab968a2618b0c5a8472ea2ab37797916 (diff) | |
| download | external_llvm-afaeb8152c79a9f3c157a614331d6919a0a0fa6a.zip external_llvm-afaeb8152c79a9f3c157a614331d6919a0a0fa6a.tar.gz external_llvm-afaeb8152c79a9f3c157a614331d6919a0a0fa6a.tar.bz2 | |
Revert ARM Scheduler Model: Add resources instructions, map resources
This reverts commit r177968. It is causing failures in a local build bot.
"fatal error: error in backend: Expected a variant SchedClass"
Original commit message:
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178028 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSchedule.td')
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 1bca554..ff1ff2f 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -64,13 +64,6 @@ def WriteALUsr : SchedWrite; // Shift by register. def WriteALUSsr : SchedWrite; // Shift by register (flag setting). def ReadAdvanceALUsr : SchedRead; // Some operands are read later. -// Define TII for use in SchedVariant Predicates. -def : PredicateProlog<[{ - const ARMBaseInstrInfo *TII = - static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo()); - (void)TII; -}]>; - //===----------------------------------------------------------------------===// // Instruction Itinerary classes used for ARM // |