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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-05 16:06:11 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-06-05 16:06:11 +0000 |
| commit | c82157378e452035e6244194f3778e4a558435f3 (patch) | |
| tree | 222e33d331ff7d2048635e4a581ca044bcfc119d /lib/Target/ARM/ARMSchedule.td | |
| parent | d87bd5627e5b78cb556d6c7b5aa76ae3d55d8acf (diff) | |
| download | external_llvm-c82157378e452035e6244194f3778e4a558435f3.zip external_llvm-c82157378e452035e6244194f3778e4a558435f3.tar.gz external_llvm-c82157378e452035e6244194f3778e4a558435f3.tar.bz2 | |
ARM sched model: Add divsion, loads, branches, vfp cvt
Add some generic SchedWrites and assign resources for Swift and Cortex A9.
Reapply of r183257. (Removed empty InstRW for division on swift)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183319 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSchedule.td')
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 2d088de..f25e9c2 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -69,6 +69,21 @@ def WriteCMP : SchedWrite; def WriteCMPsi : SchedWrite; def WriteCMPsr : SchedWrite; +// Division. +def WriteDiv : SchedWrite; + +// Loads. +def WriteLd : SchedWrite; +def WritePreLd : SchedWrite; + +// Branches. +def WriteBr : SchedWrite; +def WriteBrL : SchedWrite; +def WriteBrTbl : SchedWrite; + +// Fixpoint conversions. +def WriteCvtFP : SchedWrite; + // Define TII for use in SchedVariant Predicates. def : PredicateProlog<[{ const ARMBaseInstrInfo *TII = |