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author | Andrew Trick <atrick@apple.com> | 2013-06-15 04:50:02 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-06-15 04:50:02 +0000 |
commit | a5ce5f36d3a1e312304e8312ca64a1342f5f55a6 (patch) | |
tree | 48b5f93d3c1ec9781977edafc9a09eb43673b8a9 /lib/Target/ARM/ARMScheduleA9.td | |
parent | b86a0cdb674549d8493043331cecd9cbf53b80da (diff) | |
download | external_llvm-a5ce5f36d3a1e312304e8312ca64a1342f5f55a6.zip external_llvm-a5ce5f36d3a1e312304e8312ca64a1342f5f55a6.tar.gz external_llvm-a5ce5f36d3a1e312304e8312ca64a1342f5f55a6.tar.bz2 |
Update machine models. Specify buffer sizes for OOO processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184033 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
-rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index ce49857..74ee50b 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -1883,7 +1883,7 @@ def CortexA9Itineraries : ProcessorItineraries< // Cortex-A9 machine model for scheduling and other instruction cost heuristics. def CortexA9Model : SchedMachineModel { let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. - let MinLatency = 0; // Data dependencies are allowed within dispatch groups. + let MicroOpBufferSize = 56; // Based on available renamed registers. let LoadLatency = 2; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. @@ -1901,7 +1901,7 @@ def A9UnitALU : ProcResource<2>; def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; } def A9UnitAGU : ProcResource<1>; def A9UnitLS : ProcResource<1>; -def A9UnitFP : ProcResource<1>; +def A9UnitFP : ProcResource<1> { let BufferSize = 0; } def A9UnitB : ProcResource<1>; //===----------------------------------------------------------------------===// |