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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-21 01:12:00 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-21 01:12:00 +0000 |
| commit | d6865de2d205d501e20d312ac66463be57dc44a1 (patch) | |
| tree | 216394c7e7ce15318f375c076d41e8ecde0095a4 /lib/Target/ARM/ARMScheduleA9.td | |
| parent | d7795540d0538fb79e70d0519858d463ac4375af (diff) | |
| download | external_llvm-d6865de2d205d501e20d312ac66463be57dc44a1.zip external_llvm-d6865de2d205d501e20d312ac66463be57dc44a1.tar.gz external_llvm-d6865de2d205d501e20d312ac66463be57dc44a1.tar.bz2 | |
Add missing scheduling itineraries for transfers between core registers and VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index c223677..548bc7c 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -641,7 +641,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [1, 1]>, + [2, 1]>, // // Double-precision to Integer Move InstrItinData<IIC_fpMOVDI, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -649,7 +649,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsVFP], 0, Required>, InstrStage<2, [A9_DRegsN], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [1, 1, 1]>, + [2, 1, 1]>, // // Single-precision FP Load InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -1430,7 +1430,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [2, 1]>, + [1, 1]>, // // Integer to Double-precision Move InstrItinData<IIC_VMOVID , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, @@ -1438,7 +1438,7 @@ def CortexA9Itineraries : ProcessorItineraries< InstrStage<1, [A9_DRegsN], 0, Required>, InstrStage<3, [A9_DRegsVFP], 0, Reserved>, InstrStage<1, [A9_NPipe]>], - [2, 1, 1]>, + [1, 1, 1]>, // // Single-precision to Integer Move InstrItinData<IIC_VMOVSI , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, |