aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/ARM/ARMTargetMachine.h
diff options
context:
space:
mode:
authorEvan Cheng <evan.cheng@apple.com>2009-06-13 09:12:55 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-06-13 09:12:55 +0000
commite7d6df73530a98a5cc5f69ddfd17073b464caa57 (patch)
tree2ee5d1bb7677ae95573303bdc8a19a2e96866f82 /lib/Target/ARM/ARMTargetMachine.h
parentdaf9e02893e7e17ca2267ffd5e994f824adbb624 (diff)
downloadexternal_llvm-e7d6df73530a98a5cc5f69ddfd17073b464caa57.zip
external_llvm-e7d6df73530a98a5cc5f69ddfd17073b464caa57.tar.gz
external_llvm-e7d6df73530a98a5cc5f69ddfd17073b464caa57.tar.bz2
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMTargetMachine.h')
-rw-r--r--lib/Target/ARM/ARMTargetMachine.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h
index 916a8aa..7192c1b 100644
--- a/lib/Target/ARM/ARMTargetMachine.h
+++ b/lib/Target/ARM/ARMTargetMachine.h
@@ -71,6 +71,7 @@ public:
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addAssemblyEmitter(PassManagerBase &PM,
CodeGenOpt::Level OptLevel,