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authorEvan Cheng <evan.cheng@apple.com>2011-12-19 22:01:30 +0000
committerEvan Cheng <evan.cheng@apple.com>2011-12-19 22:01:30 +0000
commit8787c5f24e175a36f645784d533384f9f7cd86fc (patch)
tree68bba65e8851d3a846136e34754c35604e25856e /lib/Target/ARM/AsmParser
parent638905d90cf8e2601b5609e549e3fca6676fff10 (diff)
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Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn subeq r0, r1, #1 addne r0, r1, #1 into sub r0, r1, #1 addne r0, r1, #1 For targets where conditional instructions are always executed, this may be beneficial. It may remove pseudo anti-dependency in out-of-order execution CPUs. e.g. op r1, ... str r1, [r10] ; end-of-life of r1 as div result cmp r0, #65 movne r1, #44 ; raw dependency on previous r1 moveq r1, #12 If movne is unpredicated, then op r1, ... str r1, [r10] cmp r0, #65 mov r1, #44 ; r1 written unconditionally moveq r1, #12 Both mov and moveq are no longer depdendent on the first instruction. This gives the out-of-order execution engine more freedom to reorder them. This has passed entire LLVM test suite. But it has not been enabled for any ARM variant pending more performance evaluation. rdar://8951196 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146914 91177308-0d34-0410-b5e6-96231b3b80d8
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