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| author | Cameron Zwarich <zwarich@apple.com> | 2011-05-25 04:45:23 +0000 |
|---|---|---|
| committer | Cameron Zwarich <zwarich@apple.com> | 2011-05-25 04:45:23 +0000 |
| commit | 328634598fb8dbb774709aebc61a97d63f7027b3 (patch) | |
| tree | 358d6115318fe14f640dd528844eab88a991bc9d /lib/Target/ARM/Disassembler | |
| parent | 8f161c3a95d844746be41332c763fb308aae3c9c (diff) | |
| download | external_llvm-328634598fb8dbb774709aebc61a97d63f7027b3.zip external_llvm-328634598fb8dbb774709aebc61a97d63f7027b3.tar.gz external_llvm-328634598fb8dbb774709aebc61a97d63f7027b3.tar.bz2 | |
Change the order of tBX's operands so that the predicate operands come after the
target register, matching BX. I filed this bug because I was confused at first:
PR10007 - ARM branch instructions have inconsistent predicate operand placement
<http://llvm.org/bugs/show_bug.cgi?id=10007>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132041 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index c4a9f20..17ebb95 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -489,15 +489,24 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn, // BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm. if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX || Opcode==ARM::tBRIND) { - if (Opcode != ARM::tBRIND) { + if (Opcode == ARM::tBLXr_r9) { // Handling the two predicate operands before the reg operand. if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps)) return false; NumOpsAdded += 2; } + MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, getT1Rm(insn)))); NumOpsAdded += 1; + + if (Opcode == ARM::tBX) { + // Handling the two predicate operands after the reg operand. + if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps)) + return false; + NumOpsAdded += 2; + } + return true; } |