diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 22:18:07 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2011-04-05 22:18:07 +0000 |
| commit | 5438d76416bdb074bd3135a7649b31c563a05dd9 (patch) | |
| tree | 566905a0f43eccb3f31acc4df7cfe9bf06f064b9 /lib/Target/ARM/Disassembler | |
| parent | 1a8b9dd7fb945ab78232f3853219cc693bcb5fad (diff) | |
| download | external_llvm-5438d76416bdb074bd3135a7649b31c563a05dd9.zip external_llvm-5438d76416bdb074bd3135a7649b31c563a05dd9.tar.gz external_llvm-5438d76416bdb074bd3135a7649b31c563a05dd9.tar.bz2 | |
ARM disassembler was erroneously accepting an invalid RSC instruction.
Added checks for regs which should not be 15.
rdar://problem/9237734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 786e001..db76c11 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -1072,6 +1072,12 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn, if (slice(insn, 7, 7)) return false; + // A8.6.3 ADC (register-shifted register) + // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; + if (decodeRd(insn) == 15 || decodeRn(insn) == 15 || + decodeRm(insn) == 15 || decodeRs(insn) == 15) + return false; + // Register-controlled shifts: [Rm, Rs, shift]. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRs(insn)))); |