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authorOwen Anderson <resistor@mac.com>2011-08-08 20:42:17 +0000
committerOwen Anderson <resistor@mac.com>2011-08-08 20:42:17 +0000
commit6d74631062e4464326eb5c680a4d62d340fa42eb (patch)
tree277be81c9b1be1fe1bf8b5add9e35991c81c544e /lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
parent2cb1dfa4464c8dc551d93e0ce34d7a2f797304db (diff)
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Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp')
-rw-r--r--lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp13
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index 2caf548..e047fb8 100644
--- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -294,6 +294,9 @@ public:
unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const;
+ unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op,
+ SmallVectorImpl<MCFixup> &Fixups) const;
+
unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
unsigned EncodedValue) const;
unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI,
@@ -440,6 +443,16 @@ EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
return isAdd;
}
+uint32_t ARMMCCodeEmitter::
+getThumbSRImmOpValue(const MCInst &MI, unsigned OpIdx,
+ SmallVectorImpl<MCFixup> &Fixups) const {
+ const MCOperand &MO = MI.getOperand(OpIdx);
+ assert(MO.isImm() && "Expected constant shift!");
+ int val = MO.getImm();
+ return (val == 32) ? 0 : val;
+}
+
+
/// getBranchTargetOpValue - Helper function to get the branch target operand,
/// which is either an immediate or requires a fixup.
static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,