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| author | Richard Barton <richard.barton@arm.com> | 2012-04-25 18:00:18 +0000 |
|---|---|---|
| committer | Richard Barton <richard.barton@arm.com> | 2012-04-25 18:00:18 +0000 |
| commit | b56e4115ed33dae56108ed4ce88ee3a0e0392bfc (patch) | |
| tree | a5cd9bc1b730743e650a2dd96debc46e500e03f8 /lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | |
| parent | bdbf0154769dd2f2565068a51fd49e4be0005f55 (diff) | |
| download | external_llvm-b56e4115ed33dae56108ed4ce88ee3a0e0392bfc.zip external_llvm-b56e4115ed33dae56108ed4ce88ee3a0e0392bfc.tar.gz external_llvm-b56e4115ed33dae56108ed4ce88ee3a0e0392bfc.tar.bz2 | |
Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155565 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index 10d1c48..1589a5d 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -1192,8 +1192,7 @@ getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, // Encode shift_imm bit[11:7]. Binary |= SBits << 4; unsigned Offset = ARM_AM::getSORegOffset(MO1.getImm()); - assert(Offset && "Offset must be in range 1-32!"); - if (Offset == 32) Offset = 0; + assert(Offset < 32 && "Offset must be in range 0-31!"); return Binary | (Offset << 7); } |