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| author | Tim Northover <Tim.Northover@arm.com> | 2012-09-22 11:18:12 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2012-09-22 11:18:12 +0000 |
| commit | 93c7c449a1351542fa5a275587187154dbedb8e0 (patch) | |
| tree | 090aa4c36f20481371bbe181268f9adf30736a57 /lib/Target/ARM/MCTargetDesc | |
| parent | 23bd47c2d6d3c0735736bd0994ae116f534d9992 (diff) | |
| download | external_llvm-93c7c449a1351542fa5a275587187154dbedb8e0.zip external_llvm-93c7c449a1351542fa5a275587187154dbedb8e0.tar.gz external_llvm-93c7c449a1351542fa5a275587187154dbedb8e0.tar.bz2 | |
Fix the handling of edge cases in ARM shifted operands.
This patch fixes load/store instructions to handle less common cases
like "asr #32", "rrx" properly throughout the MC layer.
Patch by Chris Lidbury.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/MCTargetDesc')
| -rw-r--r-- | lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index dde7285..d0e127a 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -934,6 +934,10 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); unsigned SBits = getShiftOp(ShOp); + // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift + // amount. However, it would be an easy mistake to make so check here. + assert((ShImm & ~0x1f) == 0 && "Out of range shift amount"); + // {16-13} = Rn // {12} = isAdd // {11-0} = shifter |