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author | Jim Grosbach <grosbach@apple.com> | 2011-06-30 23:38:17 +0000 |
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committer | Jim Grosbach <grosbach@apple.com> | 2011-06-30 23:38:17 +0000 |
commit | 2a7b41ba4d3eb3c6003f6768dc20b28d83eac265 (patch) | |
tree | 74d0d6ab330b8b4317e30390e0145a8b6bfe934e /lib/Target/ARM/Thumb1InstrInfo.cpp | |
parent | 73744df0c467895bac9e25d5c62f34a0a8fcc4f9 (diff) | |
download | external_llvm-2a7b41ba4d3eb3c6003f6768dc20b28d83eac265.zip external_llvm-2a7b41ba4d3eb3c6003f6768dc20b28d83eac265.tar.gz external_llvm-2a7b41ba4d3eb3c6003f6768dc20b28d83eac265.tar.bz2 |
Refact ARM Thumb1 tMOVr instruction family.
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb1InstrInfo.cpp')
-rw-r--r-- | lib/Target/ARM/Thumb1InstrInfo.cpp | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/lib/Target/ARM/Thumb1InstrInfo.cpp b/lib/Target/ARM/Thumb1InstrInfo.cpp index 614ba81..218311d 100644 --- a/lib/Target/ARM/Thumb1InstrInfo.cpp +++ b/lib/Target/ARM/Thumb1InstrInfo.cpp @@ -36,17 +36,7 @@ void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { - bool tDest = ARM::tGPRRegClass.contains(DestReg); - bool tSrc = ARM::tGPRRegClass.contains(SrcReg); - unsigned Opc = ARM::tMOVgpr2gpr; - if (tDest && tSrc) - Opc = ARM::tMOVr; - else if (tSrc) - Opc = ARM::tMOVtgpr2gpr; - else if (tDest) - Opc = ARM::tMOVgpr2tgpr; - - AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) .addReg(SrcReg, getKillRegState(KillSrc))); assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && "Thumb1 can only copy GPR registers"); |