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| author | Stephen Hines <srhines@google.com> | 2012-03-05 14:40:54 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2012-03-05 14:40:54 -0800 |
| commit | c02a5c5e8d9c1fd2a20ad4aed40f328564e95b40 (patch) | |
| tree | 9a892d465bc8a229322b6c296c346250a95ecd6c /lib/Target/ARM/Thumb2InstrInfo.cpp | |
| parent | 2987cbcdaef9e14f635b6f9ac32c58ff26a2fc0f (diff) | |
| parent | c3384c93c0e4c50da4ad093f08997507f9281c75 (diff) | |
| download | external_llvm-c02a5c5e8d9c1fd2a20ad4aed40f328564e95b40.zip external_llvm-c02a5c5e8d9c1fd2a20ad4aed40f328564e95b40.tar.gz external_llvm-c02a5c5e8d9c1fd2a20ad4aed40f328564e95b40.tar.bz2 | |
Merge branch 'upstream' into merge-20120305
Conflicts:
lib/Support/Atomic.cpp
Change-Id: I563b3bc2a82942ccbae5bed42e53b9149a8bf3a0
Diffstat (limited to 'lib/Target/ARM/Thumb2InstrInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb2InstrInfo.cpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index 7ec3c0e..6cb182a 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -1,4 +1,4 @@ -//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===// +//===-- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information -------------===// // // The LLVM Compiler Infrastructure // @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/MC/MCInst.h" #include "llvm/Support/CommandLine.h" using namespace llvm; @@ -34,6 +35,13 @@ Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI), RI(*this, STI) { } +/// getNoopForMachoTarget - Return the noop instruction to use for a noop. +void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { + NopInst.setOpcode(ARM::tNOP); + NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); + NopInst.addOperand(MCOperand::CreateReg(0)); +} + unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const { // FIXME return 0; @@ -586,7 +594,7 @@ Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI, ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg); if (!(NCC == CC || NCC == OCC) || NMI->modifiesRegister(SrcReg, &TRI) || - NMI->definesRegister(ARM::CPSR)) + NMI->modifiesRegister(ARM::CPSR, &TRI)) break; if (++NumInsts == 4) // Too many in a row! |