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authorJim Grosbach <grosbach@apple.com>2013-08-26 20:22:05 +0000
committerJim Grosbach <grosbach@apple.com>2013-08-26 20:22:05 +0000
commit383a810b129aa5120d6a7f6e88e141ec4a45f61b (patch)
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ARM: Constrain regclass for TSTri instruction.
Get the register class right for the TST instruction. This keeps the machine verifier happy, enabling us to turn it on for another test. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8
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