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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-28 03:11:27 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-08-28 03:11:27 +0000 |
| commit | cff9baa95273bc279bf5fadb9e27afbd25cca20b (patch) | |
| tree | 730875c1eeb110a771f0879c8371beca62adf957 /lib/Target/ARM/Thumb2SizeReduction.cpp | |
| parent | 273956d8c6eed86c8b4d616ecb86f7ff17e127d4 (diff) | |
| download | external_llvm-cff9baa95273bc279bf5fadb9e27afbd25cca20b.zip external_llvm-cff9baa95273bc279bf5fadb9e27afbd25cca20b.tar.gz external_llvm-cff9baa95273bc279bf5fadb9e27afbd25cca20b.tar.bz2 | |
Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."
This wasn't the right way to enforce ordering of atomics.
We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2SizeReduction.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb2SizeReduction.cpp | 26 |
1 files changed, 5 insertions, 21 deletions
diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp index 796927c..f18f491 100644 --- a/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -114,22 +114,6 @@ namespace { { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1 }, { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1 }, { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1 }, - - // At this point it is safe to translate acquire loads to normal loads. - // There is no risk of reordering loads. - { ARM::ATOMIC_t2LDRi12, - ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1 }, - { ARM::ATOMIC_t2LDRs, - ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1 }, - { ARM::ATOMIC_t2LDRBi12, - ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1 }, - { ARM::ATOMIC_t2LDRBs, - ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1 }, - { ARM::ATOMIC_t2LDRHi12, - ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1 }, - { ARM::ATOMIC_t2LDRHs, - ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1 }, - { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1 }, { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1 }, { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1 }, @@ -357,7 +341,7 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, switch (Entry.WideOpc) { default: llvm_unreachable("Unexpected Thumb2 load / store opcode!"); - case ARM::t2LDRi12: case ARM::ATOMIC_t2LDRi12: + case ARM::t2LDRi12: case ARM::t2STRi12: if (MI->getOperand(1).getReg() == ARM::SP) { Opc = Entry.NarrowOpc2; @@ -369,7 +353,7 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, HasImmOffset = true; HasOffReg = false; break; - case ARM::t2LDRBi12: case ARM::ATOMIC_t2LDRBi12: + case ARM::t2LDRBi12: case ARM::t2STRBi12: HasImmOffset = true; HasOffReg = false; @@ -380,9 +364,9 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, HasImmOffset = true; HasOffReg = false; break; - case ARM::t2LDRs: case ARM::ATOMIC_t2LDRs: - case ARM::t2LDRBs: case ARM::ATOMIC_t2LDRBs: - case ARM::t2LDRHs: case ARM::ATOMIC_t2LDRHs: + case ARM::t2LDRs: + case ARM::t2LDRBs: + case ARM::t2LDRHs: case ARM::t2LDRSBs: case ARM::t2LDRSHs: case ARM::t2STRs: |