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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-09-13 01:12:15 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-09-13 01:12:15 +0000 |
| commit | 02791b0d5c7fe12bf1ada874da30dd5d0440bc98 (patch) | |
| tree | db76c76094a34d70d6b62d58856e11579b2b05a0 /lib/Target/ARM | |
| parent | daf700156a4b1aec6f85be6f611f2f949b154f75 (diff) | |
| download | external_llvm-02791b0d5c7fe12bf1ada874da30dd5d0440bc98.zip external_llvm-02791b0d5c7fe12bf1ada874da30dd5d0440bc98.tar.gz external_llvm-02791b0d5c7fe12bf1ada874da30dd5d0440bc98.tar.bz2 | |
Fix merge problem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81658 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index d5b1fac..20a7355 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -347,13 +347,6 @@ def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2]; } -// Subset of QPR that have 32-bit SPR subregs. -def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], - 128, - [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]> { - let SubRegClassList = [SPR, SPR, SPR, SPR, DPR, DPR]; -} - // Condition code registers. def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; |