aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/ARM
diff options
context:
space:
mode:
authorEric Christopher <echristo@apple.com>2010-10-15 22:32:37 +0000
committerEric Christopher <echristo@apple.com>2010-10-15 22:32:37 +0000
commit315030ca74f7c3cf8bf7f7d29da667ac9fc45bb0 (patch)
treec33ac8d94a61847749748b64222d77f549f0f821 /lib/Target/ARM
parent2695d8edd132b19e6a598e0a784205cdc4c12d09 (diff)
downloadexternal_llvm-315030ca74f7c3cf8bf7f7d29da667ac9fc45bb0.zip
external_llvm-315030ca74f7c3cf8bf7f7d29da667ac9fc45bb0.tar.gz
external_llvm-315030ca74f7c3cf8bf7f7d29da667ac9fc45bb0.tar.bz2
Fix else if -> if in store machinery.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116628 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r--lib/Target/ARM/ARMFastISel.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 4650e03..901cb57 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -838,7 +838,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
TLI.getRegClassFor(VT), TM.getRegisterInfo());
// The thumb addressing mode has operands swapped from the arm addressing
// mode, the floating point one only has two operands.
- if (isFloat || isThumb)
+ else if (isFloat || isThumb)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(StrOpc))
.addReg(SrcReg).addReg(Base.Reg).addImm(Offset));