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author | Andrew Trick <atrick@apple.com> | 2013-01-09 03:36:49 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-01-09 03:36:49 +0000 |
commit | 47579cf390c42e0577519e0a2b6044baece9df00 (patch) | |
tree | 2744c5de5c5c825a168a20f90b9e099d8feaaf88 /lib/Target/ARM | |
parent | 2af949ddddfaf2feb4a446c754e09d2d8c207ce4 (diff) | |
download | external_llvm-47579cf390c42e0577519e0a2b6044baece9df00.zip external_llvm-47579cf390c42e0577519e0a2b6044baece9df00.tar.gz external_llvm-47579cf390c42e0577519e0a2b6044baece9df00.tar.bz2 |
MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.
I converted some in-order scheduling tests to A2. Hal is working on
more test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 404634f..4191931 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -1887,6 +1887,9 @@ def CortexA9Model : SchedMachineModel { let LoadLatency = 2; // Optimistic load latency assuming bypass. // This is overriden by OperandCycles if the // Itineraries are queried instead. + let ILPWindow = 10; // Don't reschedule small blocks to hide + // latency. Minimum latency requirements are already + // modeled strictly by reserving resources. let MispredictPenalty = 8; // Based on estimate of pipeline depth. let Itineraries = CortexA9Itineraries; |