1. Support ELF pcrel relocations for movw/movt:

  R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123294 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 49 insertions, 5 deletions

diff --git a/lib/Target/ARM/ARMAsmBackend.cpp b/lib/Target/ARM/ARMAsmBackend.cpp
index c72e790..0d5a9af 100644
--- a/lib/Target/ARM/ARMAsmBackend.cpp
+++ b/lib/Target/ARM/ARMAsmBackend.cpp
@@ -78,6 +78,8 @@ public:
 { "fixup_arm_thumb_bcc",     1,             8,  MCFixupKindInfo::FKF_IsPCRel },
 { "fixup_arm_movt_hi16",     0,            16,  0 },
 { "fixup_arm_movw_lo16",     0,            16,  0 },
+{ "fixup_arm_movt_hi16_pcrel", 0,          16,  MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_arm_movw_lo16_pcrel", 0,          16,  MCFixupKindInfo::FKF_IsPCRel },
     };
 
     if (Kind < FirstTargetFixupKind)
@@ -156,7 +158,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
   case FK_Data_4:
     return Value;
   case ARM::fixup_arm_movt_hi16:
-  case ARM::fixup_arm_movw_lo16: {
+  case ARM::fixup_arm_movw_lo16:
+  case ARM::fixup_arm_movt_hi16_pcrel:
+  case ARM::fixup_arm_movw_lo16_pcrel: {
     unsigned Hi4 = (Value & 0xF000) >> 12;
     unsigned Lo12 = Value & 0x0FFF;
     // inst{19-16} = Hi4;
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index d1a975d..cce1576 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -189,10 +189,10 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
     int64_t Imm = MO.getImm();
     O << '#';
     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
-        (TF == ARMII::MO_LO16))
+        (TF & ARMII::MO_LO16))
       O << ":lower16:";
     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
-             (TF == ARMII::MO_HI16))
+             (TF & ARMII::MO_HI16))
       O << ":upper16:";
     O << Imm;
     break;
diff --git a/lib/Target/ARM/ARMFixupKinds.h b/lib/Target/ARM/ARMFixupKinds.h
index 3e0bd0e..12efcb2 100644
--- a/lib/Target/ARM/ARMFixupKinds.h
+++ b/lib/Target/ARM/ARMFixupKinds.h
@@ -74,6 +74,11 @@ enum Fixups {
   fixup_arm_movt_hi16, // :upper16:
   fixup_arm_movw_lo16, // :lower16:
 
+  // It is possible to create an "immediate" that happens to be pcrel.
+  // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC
+  fixup_arm_movt_hi16_pcrel, // :upper16:
+  fixup_arm_movw_lo16_pcrel, // :lower16:
+
   // Marker
   LastTargetFixupKind,
   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 0e69221..4b328ee 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -626,6 +626,32 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx,
   return Binary;
 }
 
+// FIXME: This routine needs to handle more MCExpr types
+static const MCSymbolRefExpr *FindLHSymExpr(const MCExpr *E) {
+  // recurse left child until finding a MCSymbolRefExpr
+  switch (E->getKind()) {
+  case MCExpr::SymbolRef:
+    return cast<MCSymbolRefExpr>(E);
+  case MCExpr::Binary:
+    return FindLHSymExpr(cast<MCBinaryExpr>(E)->getLHS());
+  default:
+    return NULL;
+  }
+}
+
+// FIXME: This routine assumes that a binary
+// expression will always result in a PCRel expression
+// In reality, its only true if one or more subexpressions
+// is itself a PCRel (i.e. "." in asm or some other pcrel construct)
+// but this is good enough for now.
+static bool EvaluateAsPCRel(const MCExpr *Expr) {
+  switch (Expr->getKind()) {
+  case MCExpr::SymbolRef: return false;
+  case MCExpr::Binary: return true;
+  default: assert(0 && "Unexpected expression type");
+  }
+}
+
 uint32_t ARMMCCodeEmitter::
 getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
                   SmallVectorImpl<MCFixup> &Fixups) const {
@@ -635,18 +661,27 @@ getMovtImmOpValue(const MCInst &MI, unsigned OpIdx,
   if (MO.isImm()) {
     return static_cast<unsigned>(MO.getImm());
   } else if (const MCSymbolRefExpr *Expr =
-             dyn_cast<MCSymbolRefExpr>(MO.getExpr())) {
+             FindLHSymExpr(MO.getExpr())) {
+    // FIXME: :lower16: and :upper16: should be applicable to
+    // to whole expression, not just symbolrefs
+    // Until that change takes place, this hack is required to
+    // generate working code.
+    const MCExpr *OrigExpr = MO.getExpr();
     MCFixupKind Kind;
     switch (Expr->getKind()) {
     default: assert(0 && "Unsupported ARMFixup");
     case MCSymbolRefExpr::VK_ARM_HI16:
       Kind = MCFixupKind(ARM::fixup_arm_movt_hi16);
+      if (EvaluateAsPCRel(OrigExpr)) 
+        Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel);
       break;
     case MCSymbolRefExpr::VK_ARM_LO16:
       Kind = MCFixupKind(ARM::fixup_arm_movw_lo16);
+      if (EvaluateAsPCRel(OrigExpr)) 
+        Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel);
       break;
     }
-    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
+    Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind));
     return 0;
   };
   llvm_unreachable("Unsupported MCExpr type in MCOperand!");