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author | Sylvestre Ledru <sylvestre@debian.org> | 2012-09-27 10:14:43 +0000 |
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committer | Sylvestre Ledru <sylvestre@debian.org> | 2012-09-27 10:14:43 +0000 |
commit | 94c22716d60ff5edf6a98a3c67e0faa001be1142 (patch) | |
tree | 2442b2b9658c29e72b1dd7abae926751854c68dc /lib/Target/ARM | |
parent | 7e2c793a2b5c746344652b6579e958ee42fafdcc (diff) | |
download | external_llvm-94c22716d60ff5edf6a98a3c67e0faa001be1142.zip external_llvm-94c22716d60ff5edf6a98a3c67e0faa001be1142.tar.gz external_llvm-94c22716d60ff5edf6a98a3c67e0faa001be1142.tar.bz2 |
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 2 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 | ||||
-rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 8 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 2 | ||||
-rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 6 |
5 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 1458e33..8933a02 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -276,7 +276,7 @@ ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { if (TII.isPredicable(MI) || isARMNEONPred(MI)) AddDefaultPred(MIB); - // Do we optionally set a predicate? Preds is size > 0 if the predicate + // Do we optionally set a predicate? Preds is size > 0 iff the predicate // defines CPSR. All other OptionalDefines in ARM are the CCR register. bool CPSR = false; if (DefinesOptionalPredicate(MI, &CPSR)) { diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index e9f0c8a..1eea0cc 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -2117,7 +2117,7 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N, if (N->getOpcode() == ISD::AND) { if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) { - // The immediate is a mask of the low bits if imm & (imm+1) == 0 + // The immediate is a mask of the low bits iff imm & (imm+1) == 0 if (And_imm & (And_imm + 1)) return NULL; diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 33c4835..f8455a4 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -727,7 +727,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR - // if target supports vfp2. + // iff target supports vfp2. setOperationAction(ISD::BITCAST, MVT::i64, Custom); setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); } @@ -7692,12 +7692,12 @@ static SDValue PerformORCombine(SDNode *N, DebugLoc DL = N->getDebugLoc(); // 1) or (and A, mask), val => ARMbfi A, val, mask - // if (val & mask) == val + // iff (val & mask) == val // // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask - // 2a) if isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) + // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) // && mask == ~mask2 - // 2b) if isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) + // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) // && ~mask == mask2 // (i.e., copy a bitfield value into another bitfield of the same width) diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index ca3d6d7..e171f8b 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -698,7 +698,7 @@ def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), } // Writeback version is just a pseudo, as there's no encoding difference. -// Writeback happens if the base register is not in the destination register +// Writeback happens iff the base register is not in the destination register // list. def tLDMIA_UPD : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index a16931e..aa5ba46 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5316,7 +5316,7 @@ validateInstruction(MCInst &Inst, // instruction. We'll make the transformation in processInstruction() // if necessary. // - // Thumb LDM instructions are writeback if the base register is not + // Thumb LDM instructions are writeback iff the base register is not // in the register list. unsigned Rn = Inst.getOperand(0).getReg(); bool hasWritebackToken = @@ -7023,7 +7023,7 @@ processInstruction(MCInst &Inst, Inst.addOperand(MCOperand::CreateReg(0)); // cc_out break; case ARM::tADDi8: - // If the immediate is in the range 0-7, we want tADDi3 if Rd was + // If the immediate is in the range 0-7, we want tADDi3 iff Rd was // explicitly specified. From the ARM ARM: "Encoding T1 is preferred // to encoding T2 if <Rd> is specified and encoding T2 is preferred // to encoding T1 if <Rd> is omitted." @@ -7033,7 +7033,7 @@ processInstruction(MCInst &Inst, } break; case ARM::tSUBi8: - // If the immediate is in the range 0-7, we want tADDi3 if Rd was + // If the immediate is in the range 0-7, we want tADDi3 iff Rd was // explicitly specified. From the ARM ARM: "Encoding T1 is preferred // to encoding T2 if <Rd> is specified and encoding T2 is preferred // to encoding T1 if <Rd> is omitted." |