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authorBill Wendling <isanbard@gmail.com>2010-11-19 22:06:18 +0000
committerBill Wendling <isanbard@gmail.com>2010-11-19 22:06:18 +0000
commitba46dc06e68cf6b3708cf41b737cb485152f31be (patch)
tree70df16a9b2e262ad4c4afa69d3de29d9da040adf /lib/Target/ARM
parenta898166d3863b163ee87d69a4e4a487a5a92af43 (diff)
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Revert accidental commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119850 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r--lib/Target/ARM/ARMInstrThumb.td7
1 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 8b4abcc..c917ef6 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -191,12 +191,13 @@ def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
// The i32imm operand $val can be used by a debugger to store more information
// about the breakpoint.
-def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$imm8",
+def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
[/* For disassembly only; pattern left blank */]>,
T1Encoding<0b101111> {
- bits<8> imm8;
+ bits<8> val;
+
let Inst{9-8} = 0b10;
- let Inst{7-0} = imm8;
+ let Inst{7-0} = val;
}
// Change Processor State is a system instruction -- for disassembly only.