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authorJohnny Chen <johnny.chen@apple.com>2011-04-05 19:42:11 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-04-05 19:42:11 +0000
commitbbc65bbb90e38a4066f0d4f5b403f85c1fecdf13 (patch)
tree051fe8a9dc55ac0668d71c70a3e9aab68dfb11ef /lib/Target/ARM
parent40f16cf91d8469b8198990d2649a8cc81b558277 (diff)
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ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128913 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp12
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 993ff73..cc7f0d6 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -82,8 +82,16 @@ const char *ARMUtils::OpcodeName(unsigned Opcode) {
// FIXME: Auto-gened?
static unsigned
getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
- // For this purpose, we can treat rGPR as if it were GPR.
- if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
+ if (RegClassID == ARM::rGPRRegClassID) {
+ // Check for The register numbers 13 and 15 that are not permitted for many
+ // Thumb register specifiers.
+ if (RawRegister == 13 || RawRegister == 15) {
+ B->SetErr(-1);
+ return 0;
+ }
+ // For this purpose, we can treat rGPR as if it were GPR.
+ RegClassID = ARM::GPRRegClassID;
+ }
// See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
unsigned RegNum =