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| author | Jim Grosbach <grosbach@apple.com> | 2013-08-22 00:14:24 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2013-08-22 00:14:24 +0000 |
| commit | e2a48fbd9d1ec8bebb5b10cf8770d716f8bdda28 (patch) | |
| tree | 9d753f7bd235e224026a41ed41fb81ddb084268f /lib/Target/ARM | |
| parent | 55d4c38074145bf9f594142b6b4cdca60699f4d1 (diff) | |
| download | external_llvm-e2a48fbd9d1ec8bebb5b10cf8770d716f8bdda28.zip external_llvm-e2a48fbd9d1ec8bebb5b10cf8770d716f8bdda28.tar.gz external_llvm-e2a48fbd9d1ec8bebb5b10cf8770d716f8bdda28.tar.bz2 | |
ARM: R9 is not safe to use for tcGPR.
Indirect tail-calls shouldn't use R9 for the branch destination, as
it's not reliably a call-clobbered register.
rdar://14793425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188967 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index bb7d358..90c6a96 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -251,7 +251,7 @@ def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>; // to the saved value before the tail call, which would clobber a call address. // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of // this class and the preceding one(!) This is what we want. -def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> { +def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> { let AltOrders = [(and tcGPR, tGPR)]; let AltOrderSelect = [{ return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); |