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author | Chad Rosier <mcrosier@apple.com> | 2012-11-27 01:06:49 +0000 |
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committer | Chad Rosier <mcrosier@apple.com> | 2012-11-27 01:06:49 +0000 |
commit | fc17ddd889e3dcb608e8e97c4c791755c21d7b14 (patch) | |
tree | f7fe16bd617a3e83df4677a59aa477e57f0bded3 /lib/Target/ARM | |
parent | bc43fe1efe7e1059308480b4cd8ffffc7175debd (diff) | |
download | external_llvm-fc17ddd889e3dcb608e8e97c4c791755c21d7b14.zip external_llvm-fc17ddd889e3dcb608e8e97c4c791755c21d7b14.tar.gz external_llvm-fc17ddd889e3dcb608e8e97c4c791755c21d7b14.tar.bz2 |
[arm fast-isel] Appease the machine verifier by using the proper register
classes. The associated test case still doesn't pass, but it does have far
fewer issues.
rdar://12719844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168657 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 6611862..5de5556 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -563,7 +563,9 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) { const ConstantInt *CI = cast<ConstantInt>(C); if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; - unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32)); + const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : + &ARM::GPRRegClass; + unsigned ImmReg = createResultReg(RC); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ImmReg) .addImm(CI->getZExtValue())); @@ -2577,15 +2579,18 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, unsigned Opc; bool isBoolZext = false; + const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32); if (!SrcVT.isSimple()) return 0; switch (SrcVT.getSimpleVT().SimpleTy) { default: return 0; case MVT::i16: if (!Subtarget->hasV6Ops()) return 0; - if (isZExt) + if (isZExt) { Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH; - else + } else { Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; + RC = isThumb2 ?&ARM::rGPRRegClass : &ARM::GPRnopcRegClass; + } break; case MVT::i8: if (!Subtarget->hasV6Ops()) return 0; @@ -2597,13 +2602,14 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, case MVT::i1: if (isZExt) { Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; + RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass; isBoolZext = true; break; } return 0; } - unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32)); + unsigned ResultReg = createResultReg(RC); MachineInstrBuilder MIB; MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) .addReg(SrcReg); |