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author | Owen Anderson <resistor@mac.com> | 2011-09-12 20:36:51 +0000 |
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committer | Owen Anderson <resistor@mac.com> | 2011-09-12 20:36:51 +0000 |
commit | fd92d2e106acfbf13ed29b5d15f3a690cd8699b2 (patch) | |
tree | 2c224cc9d0fe1eaaa21685fe85723cbae0127562 /lib/Target/ARM | |
parent | 26e5285f9fc63c83222b80984c590d9676a18e4f (diff) | |
download | external_llvm-fd92d2e106acfbf13ed29b5d15f3a690cd8699b2.zip external_llvm-fd92d2e106acfbf13ed29b5d15f3a690cd8699b2.tar.gz external_llvm-fd92d2e106acfbf13ed29b5d15f3a690cd8699b2.tar.bz2 |
Fix encoding of PC-relative LDRSHW with an immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM')
-rw-r--r-- | lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 29 |
1 files changed, 19 insertions, 10 deletions
diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index e65af67..f0cb95f 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -713,17 +713,26 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, Imm12 = 0; isAdd = false ; // 'U' bit is set as part of the fixup. - assert(MO.isExpr() && "Unexpected machine operand type!"); - const MCExpr *Expr = MO.getExpr(); + if (MO.isExpr()) { + const MCExpr *Expr = MO.getExpr(); - MCFixupKind Kind; - if (isThumb2()) - Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); - else - Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); - - ++MCNumCPRelocations; + MCFixupKind Kind; + if (isThumb2()) + Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); + else + Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); + Fixups.push_back(MCFixup::Create(0, Expr, Kind)); + + ++MCNumCPRelocations; + } else { + Reg = ARM::PC; + int32_t Offset = MO.getImm(); + if (Offset < 0) { + Offset *= -1; + isAdd = false; + } + Imm12 = Offset; + } } else isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); |