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author | Chris Lattner <sabre@nondot.org> | 2007-12-31 04:13:23 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2007-12-31 04:13:23 +0000 |
commit | 84bc5427d6883f73cfeae3da640acd011d35c006 (patch) | |
tree | 5686c82a5bfacdb56c5e7dabbf24990d70aac8d3 /lib/Target/Alpha/AlphaISelDAGToDAG.cpp | |
parent | 8164a33856f35763bd6f0956dd74a26ef19e11b0 (diff) | |
download | external_llvm-84bc5427d6883f73cfeae3da640acd011d35c006.zip external_llvm-84bc5427d6883f73cfeae3da640acd011d35c006.tar.gz external_llvm-84bc5427d6883f73cfeae3da640acd011d35c006.tar.bz2 |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelDAGToDAG.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 4b756b6..0490f88 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/SSARegMap.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/Target/TargetOptions.h" @@ -200,10 +200,9 @@ private: /// GOT address into a register. /// SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { - MachineFunction* MF = BB->getParent(); unsigned GP = 0; - for(MachineFunction::livein_iterator ii = MF->livein_begin(), - ee = MF->livein_end(); ii != ee; ++ii) + for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), + ee = RegInfo->livein_end(); ii != ee; ++ii) if (ii->first == Alpha::R29) { GP = ii->second; break; @@ -216,10 +215,9 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { /// getRASaveReg - Grab the return address /// SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() { - MachineFunction* MF = BB->getParent(); unsigned RA = 0; - for(MachineFunction::livein_iterator ii = MF->livein_begin(), - ee = MF->livein_end(); ii != ee; ++ii) + for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(), + ee = RegInfo->livein_end(); ii != ee; ++ii) if (ii->first == Alpha::R26) { RA = ii->second; break; |