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author | Andrew Lenharth <andrewl@lenharth.org> | 2006-10-11 16:24:51 +0000 |
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committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-10-11 16:24:51 +0000 |
commit | b4eb092bcdf8fe8879976a293c4b269251519236 (patch) | |
tree | 9ffb719ab18f0926d663c761b9acf1288782c82d /lib/Target/Alpha/AlphaISelDAGToDAG.cpp | |
parent | 7ca56aff2257ac0acceb54f3ae7ba65458d46e67 (diff) | |
download | external_llvm-b4eb092bcdf8fe8879976a293c4b269251519236.zip external_llvm-b4eb092bcdf8fe8879976a293c4b269251519236.tar.gz external_llvm-b4eb092bcdf8fe8879976a293c4b269251519236.tar.bz2 |
Reduce the amount of state in the lowering code and drop old pattern ISel functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30881 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelDAGToDAG.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 51de4e6..b3b2461 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -193,17 +193,33 @@ private: /// GOT address into a register. /// SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { + MachineFunction* MF = BB->getParent(); + unsigned GP = 0; + for(MachineFunction::livein_iterator ii = MF->livein_begin(), + ee = MF->livein_end(); ii != ee; ++ii) + if (ii->first == Alpha::R29) { + GP = ii->second; + break; + } + assert(GP && "GOT PTR not in liveins"); return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - AlphaLowering.getVRegGP(), - MVT::i64); + GP, MVT::i64); } /// getRASaveReg - Grab the return address /// SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() { + MachineFunction* MF = BB->getParent(); + unsigned RA = 0; + for(MachineFunction::livein_iterator ii = MF->livein_begin(), + ee = MF->livein_end(); ii != ee; ++ii) + if (ii->first == Alpha::R26) { + RA = ii->second; + break; + } + assert(RA && "RA PTR not in liveins"); return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), - AlphaLowering.getVRegRA(), - MVT::i64); + RA, MVT::i64); } /// InstructionSelectBasicBlock - This callback is invoked by |