Reduce the amount of state in the lowering code and drop old pattern ISel functions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30881 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 20 insertions, 4 deletions

diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 51de4e6..b3b2461 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -193,17 +193,33 @@ private:
 /// GOT address into a register.
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
+  MachineFunction* MF = BB->getParent();
+  unsigned GP = 0;
+  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
+	ee = MF->livein_end(); ii != ee; ++ii)
+    if (ii->first == Alpha::R29) {
+      GP = ii->second;
+      break;
+    }
+  assert(GP && "GOT PTR not in liveins");
   return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), 
-                                AlphaLowering.getVRegGP(), 
-                                MVT::i64);
+                                GP, MVT::i64);
 }
 
 /// getRASaveReg - Grab the return address
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
+  MachineFunction* MF = BB->getParent();
+  unsigned RA = 0;
+  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
+	ee = MF->livein_end(); ii != ee; ++ii)
+    if (ii->first == Alpha::R26) {
+      RA = ii->second;
+      break;
+    }
+  assert(RA && "RA PTR not in liveins");
   return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
-                                AlphaLowering.getVRegRA(), 
-                                MVT::i64);
+                                RA, MVT::i64);
 }
 
 /// InstructionSelectBasicBlock - This callback is invoked by