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author | Andrew Lenharth <andrewl@lenharth.org> | 2006-06-21 15:42:36 +0000 |
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committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-06-21 15:42:36 +0000 |
commit | df97cc67a685b849f5b90bb1135fea87df4d32fd (patch) | |
tree | 502169c5c44ed0ff8e16d1fa6e2e2d53c5b40bdc /lib/Target/Alpha/AlphaISelDAGToDAG.cpp | |
parent | 1725599574de4c974230dbb88125322b53fd7f39 (diff) | |
download | external_llvm-df97cc67a685b849f5b90bb1135fea87df4d32fd.zip external_llvm-df97cc67a685b849f5b90bb1135fea87df4d32fd.tar.gz external_llvm-df97cc67a685b849f5b90bb1135fea87df4d32fd.tar.bz2 |
Add memory operand and int regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28896 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelDAGToDAG.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index bbb18cb..7443371 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -119,6 +119,24 @@ namespace { return "Alpha DAG->DAG Pattern Instruction Selection"; } + /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for + /// inline asm expressions. + virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, + char ConstraintCode, + std::vector<SDOperand> &OutOps, + SelectionDAG &DAG) { + SDOperand Op0; + switch (ConstraintCode) { + default: return true; + case 'm': // memory + Select(Op0, Op); + break; + } + + OutOps.push_back(Op0); + return false; + } + // Include the pieces autogenerated from the target description. #include "AlphaGenDAGISel.inc" |