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authorDale Johannesen <dalej@apple.com>2007-09-23 14:52:20 +0000
committerDale Johannesen <dalej@apple.com>2007-09-23 14:52:20 +0000
commite0e0fd0c2407f6cfeb591da64ad44b10ed5d6d54 (patch)
tree309842454fb97a870e0b66d8dc70bfa9ef9b17b7 /lib/Target/Alpha/AlphaISelLowering.cpp
parentc2ff95db158aaf4e8698ee9092daaa131c37f804 (diff)
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Fix PR 1681. When X86 target uses +sse -sse2,
keep f32 in SSE registers and f64 in x87. This is effectively a new codegen mode. Change addLegalFPImmediate to permit float and double variants to do different things. Adjust callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42246 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaISelLowering.cpp')
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index a3654af..45a271d 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -140,7 +140,9 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
addLegalFPImmediate(APFloat(+0.0)); //F31
+ addLegalFPImmediate(APFloat(+0.0f)); //F31
addLegalFPImmediate(APFloat(-0.0)); //-F31
+ addLegalFPImmediate(APFloat(-0.0f)); //-F31
setJumpBufSize(272);
setJumpBufAlignment(16);