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| author | Bill Wendling <isanbard@gmail.com> | 2008-12-12 00:56:36 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2008-12-12 00:56:36 +0000 |
| commit | ab55ebda1c2254f98b06e770bc2dae7d05a4a366 (patch) | |
| tree | 770f22dcefcbafbbb4a2a91a7a195d7eca15ab47 /lib/Target/Alpha/AlphaLLRP.cpp | |
| parent | 905315441ea40b068d58f5d9ff8328264af99e90 (diff) | |
| download | external_llvm-ab55ebda1c2254f98b06e770bc2dae7d05a4a366.zip external_llvm-ab55ebda1c2254f98b06e770bc2dae7d05a4a366.tar.gz external_llvm-ab55ebda1c2254f98b06e770bc2dae7d05a4a366.tar.bz2 | |
Redo the arithmetic with overflow architecture. I was changing the semantics of
ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.
Similar for SUB and MUL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60915 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaLLRP.cpp')
0 files changed, 0 insertions, 0 deletions