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authorChris Lattner <sabre@nondot.org>2006-05-04 17:21:20 +0000
committerChris Lattner <sabre@nondot.org>2006-05-04 17:21:20 +0000
commit63b3d7113d93fda622c4954c6b1d046ce029044e (patch)
treea1e0a659d24e6615f29a8184a3ae0b23ef6e6e03 /lib/Target/Alpha/AlphaRegisterInfo.cpp
parentceb408f6a263e319683209ae5c6f8d1e3e4d9b69 (diff)
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There shalt be only one "immediate" operand type!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28099 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaRegisterInfo.cpp')
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 85c9da8..95f60ed 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -234,14 +234,14 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
//inst off the SP/FP
//fix up the old:
MI.SetMachineOperandReg(i + 1, Alpha::R28);
- MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed,
+ MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate,
getLower16(Offset));
//insert the new
MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
.addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
MBB.insert(II, nMI);
} else {
- MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset);
+ MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset);
}
}