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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-18 20:31:01 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-18 20:31:01 +0000 |
| commit | 928eb49cae286c95dceecf4442997dd561c6e3b7 (patch) | |
| tree | d65ac9dd3b6f18abc632f4d186d430e075ded25a /lib/Target/Alpha | |
| parent | d65077a50901cbe55d8285bb1149eb8ba8210a58 (diff) | |
| download | external_llvm-928eb49cae286c95dceecf4442997dd561c6e3b7.zip external_llvm-928eb49cae286c95dceecf4442997dd561c6e3b7.tar.gz external_llvm-928eb49cae286c95dceecf4442997dd561c6e3b7.tar.bz2 | |
Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha')
| -rw-r--r-- | lib/Target/Alpha/AlphaSchedule.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaSchedule.td b/lib/Target/Alpha/AlphaSchedule.td index b7b4560..4dc04b8 100644 --- a/lib/Target/Alpha/AlphaSchedule.td +++ b/lib/Target/Alpha/AlphaSchedule.td @@ -53,7 +53,8 @@ def s_pseudo : InstrItinClass; //Table 24 Instruction Class Latency in Cycles //modified some -def Alpha21264Itineraries : ProcessorItineraries<[ +def Alpha21264Itineraries : ProcessorItineraries< + [L0, L1, FST0, FST1, U0, U1, FA, FM], [ InstrItinData<s_ild , [InstrStage<3, [L0, L1]>]>, InstrItinData<s_fld , [InstrStage<4, [L0, L1]>]>, InstrItinData<s_ist , [InstrStage<0, [L0, L1]>]>, |