Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 16 insertions, 18 deletions

diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index a55dd74..f0b124d 100644
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -78,8 +78,8 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
     assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
     O << TM.getRegisterInfo()->get(MO.getReg()).Name;
   } else if (MO.isImmediate()) {
-    O << MO.getImmedValue();
-    assert(MO.getImmedValue() < (1 << 30));
+    O << MO.getImm();
+    assert(MO.getImm() < (1 << 30));
   } else {
     printOp(MO);
   }
diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp
index d362f35..6d68fa9 100644
--- a/lib/Target/Alpha/AlphaCodeEmitter.cpp
+++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp
@@ -151,7 +151,7 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
   if (MO.isRegister()) {
     rv = getAlphaRegNumber(MO.getReg());
   } else if (MO.isImmediate()) {
-    rv = MO.getImmedValue();
+    rv = MO.getImm();
   } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
              || MO.isConstantPoolIndex()) {
     DOUT << MO << " is a relocated op for " << MI << "\n";
@@ -187,7 +187,7 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
     case Alpha::LDAg:
     case Alpha::LDAHg:
       Reloc = Alpha::reloc_gpdist;
-      Offset = MI.getOperand(3).getImmedValue();
+      Offset = MI.getOperand(3).getImm();
       break;
     default:
       assert(0 && "unknown relocatable instruction");
@@ -195,12 +195,12 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
     }
     if (MO.isGlobalAddress())
       MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
-                                          Reloc, MO.getGlobal(), Offset,
-                                          false, useGOT));
+                                                 Reloc, MO.getGlobal(), Offset,
+                                                 false, useGOT));
     else if (MO.isExternalSymbol())
       MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
-                                          Reloc, MO.getSymbolName(), Offset,
-                                          true));
+                                                     Reloc, MO.getSymbolName(),
+                                                     Offset, true));
     else
     MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
                                           Reloc, MO.getConstantPoolIndex(),
diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index 79d03c6..15d12c7 100644
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -67,11 +67,9 @@ namespace {
           case Alpha::STW:  case Alpha::STB:
           case Alpha::STT: case Alpha::STS:
            if (MI->getOperand(2).getReg() == Alpha::R30) {
-             if (prev[0] 
-                 && prev[0]->getOperand(2).getReg() == 
-                 MI->getOperand(2).getReg()
-                 && prev[0]->getOperand(1).getImmedValue() == 
-                 MI->getOperand(1).getImmedValue()) {
+             if (prev[0] && 
+                 prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&&
+                 prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){
                prev[0] = prev[1];
                prev[1] = prev[2];
                prev[2] = 0;
@@ -83,8 +81,8 @@ namespace {
              } else if (prev[1] 
                         && prev[1]->getOperand(2).getReg() == 
                         MI->getOperand(2).getReg()
-                        && prev[1]->getOperand(1).getImmedValue() == 
-                        MI->getOperand(1).getImmedValue()) {
+                        && prev[1]->getOperand(1).getImm() == 
+                        MI->getOperand(1).getImm()) {
                prev[0] = prev[2];
                prev[1] = prev[2] = 0;
                BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
@@ -98,8 +96,8 @@ namespace {
              } else if (prev[2] 
                         && prev[2]->getOperand(2).getReg() == 
                         MI->getOperand(2).getReg()
-                        && prev[2]->getOperand(1).getImmedValue() == 
-                        MI->getOperand(1).getImmedValue()) {
+                        && prev[2]->getOperand(1).getImm() == 
+                        MI->getOperand(1).getImm()) {
                prev[0] = prev[1] = prev[2] = 0;
                BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
                  .addReg(Alpha::R31);
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 53d8df1..bb25981 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -280,7 +280,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
     // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
     // <amt>'
     MachineInstr *Old = I;
-    uint64_t Amount = Old->getOperand(0).getImmedValue();
+    uint64_t Amount = Old->getOperand(0).getImm();
     if (Amount != 0) {
       // We need to keep the stack aligned properly.  To do this, we round the
       // amount of space needed for the outgoing arguments up to the next