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author | Sandeep Patel <deeppatel1987@gmail.com> | 2009-09-02 08:44:58 +0000 |
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committer | Sandeep Patel <deeppatel1987@gmail.com> | 2009-09-02 08:44:58 +0000 |
commit | 65c3c8f323198b99b88b109654194540cf9b3fa5 (patch) | |
tree | eb867222ef634a613f0f8df64edac4e1b46eb638 /lib/Target/Blackfin/BlackfinISelLowering.cpp | |
parent | 25f1992cf56799d3d887e7578c66d63ecba108fb (diff) | |
download | external_llvm-65c3c8f323198b99b88b109654194540cf9b3fa5.zip external_llvm-65c3c8f323198b99b88b109654194540cf9b3fa5.tar.gz external_llvm-65c3c8f323198b99b88b109654194540cf9b3fa5.tar.bz2 |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin/BlackfinISelLowering.cpp')
-rw-r--r-- | lib/Target/Blackfin/BlackfinISelLowering.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp index 1ca1fae..7c36b01 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.cpp +++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp @@ -161,7 +161,7 @@ SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { SDValue BlackfinTargetLowering::LowerFormalArguments(SDValue Chain, - unsigned CallConv, bool isVarArg, + CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, @@ -218,7 +218,7 @@ BlackfinTargetLowering::LowerFormalArguments(SDValue Chain, SDValue BlackfinTargetLowering::LowerReturn(SDValue Chain, - unsigned CallConv, bool isVarArg, + CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, DebugLoc dl, SelectionDAG &DAG) { @@ -275,7 +275,7 @@ BlackfinTargetLowering::LowerReturn(SDValue Chain, SDValue BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee, - unsigned CallConv, bool isVarArg, + CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::InputArg> &Ins, |