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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-03 19:32:30 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-03 19:32:30 +0000 |
commit | ea1c9b7bacb6d58b4fef08fb32b1a7ccef856c1e (patch) | |
tree | 0005a7b3a4d5a263f60fa7104d8e84b25da7162a /lib/Target/Blackfin/BlackfinISelLowering.cpp | |
parent | cdc0654b3e1858784fd60e99655699b84b4a8104 (diff) | |
download | external_llvm-ea1c9b7bacb6d58b4fef08fb32b1a7ccef856c1e.zip external_llvm-ea1c9b7bacb6d58b4fef08fb32b1a7ccef856c1e.tar.gz external_llvm-ea1c9b7bacb6d58b4fef08fb32b1a7ccef856c1e.tar.bz2 |
Minor stylistic cleanups in the Blackfin target.
Thanks Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77987 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin/BlackfinISelLowering.cpp')
-rw-r--r-- | lib/Target/Blackfin/BlackfinISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp index 4b1bd9d..cb68a59 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.cpp +++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp @@ -188,8 +188,8 @@ SDValue BlackfinTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, MVT RegVT = VA.getLocVT(); TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ? BF::PRegisterClass : BF::DRegisterClass; - assert(RC->contains(VA.getLocReg())); - assert(RC->hasType(RegVT)); + assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState"); + assert(RC->hasType(RegVT) && "Unexpected regclass in CCState"); unsigned Reg = MF.getRegInfo().createVirtualRegister(RC); MF.getRegInfo().addLiveIn(VA.getLocReg(), Reg); @@ -210,7 +210,7 @@ SDValue BlackfinTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, ArgValues.push_back(ArgValue); } else { - assert(VA.isMemLoc()); + assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc"); unsigned ObjSize = VA.getLocVT().getStoreSizeInBits()/8; int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset()); SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); @@ -331,10 +331,10 @@ SDValue BlackfinTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); } else { - assert(VA.isMemLoc()); + assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc"); int Offset = VA.getLocMemOffset(); - assert(Offset%4 == 0); - assert(VA.getLocVT()==MVT::i32); + assert(Offset%4 == 0 && "Unaligned LocMemOffset"); + assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type"); SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32); SDValue OffsetN = DAG.getIntPtrConstant(Offset); OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN); |