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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 17:32:10 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 17:32:10 +0000 |
commit | d950941e138455ebcd7a5f55805dcb977892e3e3 (patch) | |
tree | f9732e3dd797f8f76f0c886f57f295daeb1f1a92 /lib/Target/Blackfin/BlackfinInstrInfo.h | |
parent | 4ea480499c40cd7e28bf35cacda33ccbab2aab07 (diff) | |
download | external_llvm-d950941e138455ebcd7a5f55805dcb977892e3e3.zip external_llvm-d950941e138455ebcd7a5f55805dcb977892e3e3.tar.gz external_llvm-d950941e138455ebcd7a5f55805dcb977892e3e3.tar.bz2 |
Analog Devices Blackfin back-end.
Generate code for the Blackfin family of DSPs from Analog Devices:
http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html
We aim to be compatible with the exsisting GNU toolchain found at:
http://blackfin.uclinux.org/gf/project/toolchain
The back-end is experimental.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin/BlackfinInstrInfo.h')
-rw-r--r-- | lib/Target/Blackfin/BlackfinInstrInfo.h | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/lib/Target/Blackfin/BlackfinInstrInfo.h b/lib/Target/Blackfin/BlackfinInstrInfo.h new file mode 100644 index 0000000..ea3429c --- /dev/null +++ b/lib/Target/Blackfin/BlackfinInstrInfo.h @@ -0,0 +1,80 @@ +//===- BlackfinInstrInfo.h - Blackfin Instruction Information ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the Blackfin implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef BLACKFININSTRUCTIONINFO_H +#define BLACKFININSTRUCTIONINFO_H + +#include "llvm/Target/TargetInstrInfo.h" +#include "BlackfinRegisterInfo.h" + +namespace llvm { + + class BlackfinInstrInfo : public TargetInstrInfoImpl { + const BlackfinRegisterInfo RI; + const BlackfinSubtarget& Subtarget; + public: + explicit BlackfinInstrInfo(BlackfinSubtarget &ST); + + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As + /// such, whenever a client has an instance of instruction info, it should + /// always be able to get register info as well (through this method). + virtual const BlackfinRegisterInfo &getRegisterInfo() const { return RI; } + + virtual bool isMoveInstr(const MachineInstr &MI, + unsigned &SrcReg, unsigned &DstReg, + unsigned &SrcSubIdx, unsigned &DstSubIdx) const; + + virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; + + virtual unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; + + virtual unsigned + InsertBranch(MachineBasicBlock &MBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + const SmallVectorImpl<MachineOperand> &Cond) const; + + virtual bool copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const; + + virtual void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, bool isKill, + int FrameIndex, + const TargetRegisterClass *RC) const; + + virtual void storeRegToAddr(MachineFunction &MF, + unsigned SrcReg, bool isKill, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl<MachineInstr*> &NewMIs) const; + + virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIndex, + const TargetRegisterClass *RC) const; + + virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, + SmallVectorImpl<MachineInstr*> &NewMIs) const; + }; + +} // end namespace llvm + +#endif |