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author | Dan Gohman <gohman@apple.com> | 2009-11-19 16:35:11 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-11-19 16:35:11 +0000 |
commit | 57474fa0f6d5ba6b5797e3c4b08014168f915cc1 (patch) | |
tree | e4c6ca073be2de242049e71552a00a4e13e01bae /lib/Target/Blackfin/BlackfinRegisterInfo.td | |
parent | 90c583fff0535d441717425ad4428d85eb2a00a9 (diff) | |
download | external_llvm-57474fa0f6d5ba6b5797e3c4b08014168f915cc1.zip external_llvm-57474fa0f6d5ba6b5797e3c4b08014168f915cc1.tar.gz external_llvm-57474fa0f6d5ba6b5797e3c4b08014168f915cc1.tar.bz2 |
Fix a typo in a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89360 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin/BlackfinRegisterInfo.td')
-rw-r--r-- | lib/Target/Blackfin/BlackfinRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.td b/lib/Target/Blackfin/BlackfinRegisterInfo.td index 642d10f..d396cc8 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.td +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.td @@ -44,7 +44,7 @@ class Ra<bits<3> num, string n, list<Register> subs> : BlackfinReg<n> { let Num = num; } -// Ywo halves of 32-bit register +// Two halves of 32-bit register multiclass Rss<bits<3> group, bits<3> num, string n> { def H : Rs<group, num, 1, !strconcat(n, ".h")>; def L : Rs<group, num, 0, !strconcat(n, ".l")>; |