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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 17:39:17 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 17:39:17 +0000 |
| commit | 63cc527fbce3d1e4b47b687c404b1777fa15ffe5 (patch) | |
| tree | 0cd6b5fa5f13421e7b72aff823868b7c7a2072a6 /lib/Target/Blackfin/BlackfinRegisterInfo.td | |
| parent | 73b7bb7b07fdf63f699698d4027dd981fd46ce80 (diff) | |
| download | external_llvm-63cc527fbce3d1e4b47b687c404b1777fa15ffe5.zip external_llvm-63cc527fbce3d1e4b47b687c404b1777fa15ffe5.tar.gz external_llvm-63cc527fbce3d1e4b47b687c404b1777fa15ffe5.tar.bz2 | |
Inline assembly support for Blackfin.
We use the same constraints as GCC, including those that are slightly insane for inline assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77899 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin/BlackfinRegisterInfo.td')
| -rw-r--r-- | lib/Target/Blackfin/BlackfinRegisterInfo.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.td b/lib/Target/Blackfin/BlackfinRegisterInfo.td index 2b06fe3..642d10f 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.td +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.td @@ -281,6 +281,8 @@ def P : RegisterClass<"BF", [i32], 32, [P0, P1, P2, P3, P4, P5, FP, SP]> { def I : RegisterClass<"BF", [i32], 32, [I0, I1, I2, I3]>; def M : RegisterClass<"BF", [i32], 32, [M0, M1, M2, M3]>; +def B : RegisterClass<"BF", [i32], 32, [B0, B1, B2, B3]>; +def L : RegisterClass<"BF", [i32], 32, [L0, L1, L2, L3]>; def DP : RegisterClass<"BF", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, R7, @@ -378,3 +380,6 @@ def AnyCC : RegisterClass<"BF", [i32], 8, [CC, NCC]> { def StatBit : RegisterClass<"BF", [i1], 8, [AZ, AN, CC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS]>; } + +// Should be i40, but that isn't defined. It is not a legal type yet anyway. +def Accu : RegisterClass<"BF", [i64], 64, [A0, A1]>; |